There is an increasing interest in the electronics industry in a high-density memory cell device. Research and development efforts are being therefore made for dynamic random access memory devices using one switching transistor and one storage capacitor structure which is considered to be the feasible approach to increase the memory cell density. However, there are still many problems to implement a ultra-high-density memory device on a single semiconductor chip. For better understanding of the features and advantages of a semiconductor memory device according to the present invention over prior-art semiconductor memory devices, description will be hereinafter made with reference to FIG. 1 which shows a typical example of a storage capacitor incorporated in the prior-art memory cell of the semiconductor memory device. The storage capacitor basically comprises a lower electrode 1 formed in a major surface region of a p-type reverse-biased semiconductor substrate 2, a thin dielectric film 3 of, for example, silicon dioxide which is thermally grown in an oxidation ambient, and an upper electrode 4 of, for example, polysilicon. Though not shown in FIG. 1, the storage capacitor is arranged to be contiguous to an access transistor to form in combination a memory cell capable of storing either binary data in the form of electric charge. When the memory cell consisting of the storage capacitor shown in FIG. 1 and the associated access transistor (not shown) is accessed from an external device such as a microprocessor, the associated access transistor turns on to allow electric charges to flow in (write mode) or flow out (read mode) across the switching transistor and thereafter turns off to maintain the electric charges in the storage capacitor.
The prior-art memory cell structure has a problem in soft errors. On the completion of fabricating the memory cell array and peripheral circuits on the semiconductor substrate 2, the semiconductor chip is assembled and packaged for completion of the memory cell device. The packaging materials contain some impurities such as uranium and thorium atoms which produce .alpha.-particles emitted by the decay thereof. These .alpha.-particles in turn produce electrons and holes during the penetrations through the semiconductor substrate 2 as well as projections of another charged particle. As illustrated in FIG. 1, the substrate 2 is biased to a negative voltage level, only the holes produced by the .alpha.-particles and another charged particle are attracted to the negative voltage source, then remaining the electrons in the semiconductor substrate 2. The remaining electrons cause the binary data stored in the memory cell to be destroyed. In order to prevent the binary data stored in the memory cell from destruction caused by the .alpha.-particles, it is necessary to use a high quality packaging material or to apply an .alpha.-absorbing coating over the memory cell array. However, these solutions increase the production cost and has problems in complexity in the process of device fabrication.
A trench capacitor is seen in "BURIED STORAGE ELECTRODE (BSE) CELL FOR MEGABIT DRAMS", IEDM Technical Digest 1985, pp. 710 to 713, but this paper has been written by authors including the inventor.
The present invention contemplates elimination of these problems inherent in the prior-art memory cell device.